BGA Failures during Cold Step Stress testing in HALT

Cracked BGA Joint

I recently had the opportunity to do HALT on several samples of a product that was densely populated with BGA mounted devices. During the testing I was surprised to find many hard failures in the devices during cold thermal step testing, in the range of -40 to -70°C. Typically, cold step testing on PCBs isn’t destructive. This puzzled me, so I did a quick literature search to see what I could find on cold thermal stresses and BGA reliability. I thought I would share the results here, and see if there were any comments or correlating experiences.

Of course, the bulk of the literature is focused on thermal cycle testing rather than stepping to thermal extremes, but there was some interesting data on the effects of dwell duration and the relative stresses of cold vs hot dwells, as well as ramp rate effects. In general, there was agreement that the cold dwells were more stressful than the hot dwells, and that rapid thermal change rates were much more stressful than the typical 2 to 4°C/min ramp rates used in cycling. Perhaps just the shear density of BGAs on the devices I tested accounted for the surprising number of cold failures versus my past experience.

Here are links to a few papers that I found interesting. First, I have “Accelerated Thermal Cycling and Failure Mechanisms For BGA and CSP Assemblies”, by Reza Ghaffarian, Ph.D. with the Jet Propulsion Laboratory. His paper can be found here:

His conclusions include:

“Near-thermal shock conditions induced the most damage on CBGA assemblies compared to thermal cycling. Up to 50 percent reduction in cycles to failure were observed when heating/cooling rates significantly increased for thermal cycling in the range of –55 to 125°C.”

Note that in this paper, the ‘near-thermal shock’ conditions were change rates of 10°C to 15°C per minute, relatively slow compared to the 60°C + per minute we get used to using in HALT!

Dr. Ghaffarian also did a presentation on the material in the paper, with a few extra bits of information. It can be found at:

Outside of the material in the paper, it includes a brief description of the effects of vibration, including the fact that vibration induced different failure mechanisms that thermal cycling. Given this information, testing in a combined thermal and vibration environment makes even more sense. It also includes a bullet point describing the effect of board stiffness on BGA reliability.

Finally, I looked at “Effects of Dwell Time and Ramp Rate on Lead-Free Solder Joints in FCBGA Packages”, by Xuejun Fan, George Raiser and Vasu S. Vasudevan with Intel Corporation. It can be found at:

The conclusions in this paper correlate with the results from the Ghaffarian paper and presentation as far as the relative stresses induced by thermal shock vs. thermal ramps. Note that ‘Thermal Shock” in this paper comparable to the change rates achieved in a HALT system, 60°C to 90°C per minute. He also concluded that the cold thermal dwell was very effective for increasing damage accumulation:

“The results clearly show that the accumulated strain energy density with shorter ramp time is much greater than that with longer ramp time. Therefore, thermal shock is predicted to impose more damage than thermal cycling on the solder joint. From Fig. 1, it can be seen that the inelastic strain energy density is primarily accumulated during the ramp portions. Larger temperature ranges of ΔT would cause more damage accumulation during the ramp portion. This confirms that ΔT is one of most significant parameters impacting solder joint reliability. There is also a very large contribution to the total strain energy density during the low-temperature dwell time portion. However, results show that during the high temperature dwell-time portion, the contributions are negligible. “

I hope you find these interesting. Please feel free to share opinions, experiences or reference materials on the topic of cold thermal dwells on BGA fatigue.

Thanks! And remember – if it isn’t broken, you’re not done yet!

Neill Doertenbach, Senior Reliability Engineer, Qualmark Corporation

[email protected], 303-589-1326


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